A 3-5 GHz LNA in 0.25μm SOI CMOS process for implantable WBANs
- Publication Type:
- Conference Proceeding
- Citation:
- Midwest Symposium on Circuits and Systems, 2012, pp. 766 - 769
- Issue Date:
- 2012-10-16
Closed Access
Filename | Description | Size | |||
---|---|---|---|---|---|
06292133.pdf | Published version | 399.18 kB |
Copyright Clearance Process
- Recently Added
- In Progress
- Closed Access
This item is closed access and not available.
A low-voltage, low-power single-ended LNA is implemented in a 0.25μm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of -10 dBm and small-signal gain of 19.2 dB within the 3-5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm 2. Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs. © 2012 IEEE.
Please use this identifier to cite or link to this item: