Experimental validation of nine-level switched-capacitor inverter topology with high voltage gain

Mohamed Ali, JS; Siddique, MD; Mekhilef, S; Yang, Y; Siwakoti, Y; Blaabjerg, F

Experimental validation of nine-level switched-capacitor inverter topology with high voltage gain

Mohamed Ali, JS Siddique, MD Mekhilef, S Yang, Y Siwakoti, Y

Blaabjerg, F

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Publisher:: WILEY
Publication Type:: Journal Article
Citation:: International Journal of Circuit Theory and Applications, 2021, 49, (8), pp. 2479-2493
Issue Date:: 2021-08-01

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Field	Value	Language
dc.contributor.author	Mohamed Ali, JS
dc.contributor.author	Siddique, MD
dc.contributor.author	Mekhilef, S
dc.contributor.author	Yang, Y
dc.contributor.author	Siwakoti, Y https://orcid.org/0000-0002-3869-412X
dc.contributor.author	Blaabjerg, F
dc.date.accessioned	2022-06-01T01:12:42Z
dc.date.available	2022-06-01T01:12:42Z
dc.date.issued	2021-08-01
dc.identifier.citation	International Journal of Circuit Theory and Applications, 2021, 49, (8), pp. 2479-2493
dc.identifier.issn	0098-9886
dc.identifier.issn	1097-007X
dc.identifier.uri	http://hdl.handle.net/10453/157853
dc.description.abstract	This paper proposes a new switched-capacitor nine-level (9L) inverter with reduced switch count. In the proposed topology, floating capacitor (FC) is employed as a voltage booster, and it does not need any additional sensors to maintain the voltage across the FC. Due to additional FC, the number of dc sources and voltage stress on switches is reduced. Moreover, the proposed topology can be cascaded to achieve more voltage levels. Various parameters are considered in the comparison of the proposed topology with other recent switched-capacitor topologies. Simulation and experimental results demonstrate the performance with different load and modulation index variations.
dc.language	English
dc.publisher	WILEY
dc.relation.ispartof	International Journal of Circuit Theory and Applications
dc.relation.isbasedon	10.1002/cta.3004
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject	0906 Electrical and Electronic Engineering
dc.subject.classification	Electrical & Electronic Engineering
dc.title	Experimental validation of nine-level switched-capacitor inverter topology with high voltage gain
dc.type	Journal Article
utslib.citation.volume	49
utslib.for	0906 Electrical and Electronic Engineering
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2022-06-01T01:12:34Z
pubs.issue	8
pubs.publication-status	Published
pubs.volume	49
utslib.citation.issue	8

Abstract:

This paper proposes a new switched-capacitor nine-level (9L) inverter with reduced switch count. In the proposed topology, floating capacitor (FC) is employed as a voltage booster, and it does not need any additional sensors to maintain the voltage across the FC. Due to additional FC, the number of dc sources and voltage stress on switches is reduced. Moreover, the proposed topology can be cascaded to achieve more voltage levels. Various parameters are considered in the comparison of the proposed topology with other recent switched-capacitor topologies. Simulation and experimental results demonstrate the performance with different load and modulation index variations.

Please use this identifier to cite or link to this item:

http://hdl.handle.net/10453/157853